SH7604 Datasheet, PDF (259/633 Pages) Hitachi Semiconductor – Hardware Manual

9.2.7 DMA Operation Register (DMAOR)
Bit: 31
30
29
…
11
10
9
8
Bit name: —
—
—
…
—
—
—
—
Initial value: 0
0
0
…
0
0
0
0
R/W: R
R
R
…
R
R
R
R
Bit: 7
6
5
Bit name: —
—
—
Initial value: 0
0
0
R/W: R
R
R
Note: Only 0 can be written, to clear the flag.
4
3
2
1
0
—
PR
AE
NMIF DMIE
0
0
0
0
0
R
R/W R/(W)* R/(W)* R/W
The DMA operation register (DMAOR) is a 32-bit read/write register that controls the DMA
transfer mode. It also indicates the DMA transfer status. Only the lower four of the 32 bits are
valid. DMAOR is written as a 32-bit value, including the upper 28 bits. Write the initial values to
the upper 28 bits. These bits always read 0. DMAOR is initialized to H'00000000 by a reset and in
standby mode.
• Bits 31 to 4—Reserved: These bits always read 0. The write value should always be 0.
• Bit 3—Priority Mode Bit (PR): Selects the priority level between channels when there are
transfer requests for multiple channels. It is initialized to 0 by a reset and in standby mode. Its
value is retained during a module standby.
Bit 3: PR
0
1
Description
Fixed priority (channel 0 > channel 1)
(Initial value)
Round-robin (Top priority shifts to bottom after each transfer. The
priority for the first DMA transfer after a reset is channel 1 > channel 0)
• Bit 2—Address Error Flag Bit (AE): This flag indicates that an address error has occurred in
the DMAC. When the AE bit is set to 1, DMA transfer cannot be enabled even if the DE bit in
the DMA channel control register (CHCR) is set to 1. To clear the AE bit, read 1 from it and
then write 0. Operation is performed up to the DMAC transfer being executed when the
address error occurred. AE is initialized to 0 by a reset and in standby mode.
Bit 2: AE
0
1
Description
No DMAC address error
To clear the AE bit, read 1 from it and then write 0
Address error by DMAC
(Initial value)
243