SH7604 Datasheet, PDF (524/633 Pages) Hitachi Semiconductor – Hardware Manual

CKIO
Upper
address
Lower
address
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31–D0
T_r
T_rw T_c
T_w T_d1 T_d2 T_d3 T_d4
t_BSD
DACKn
WAIT
RAS,
CE
CAS,
OE
t_RASD1 t_RASD1
t_CASD1 t_CASD1
CKE
Notes: 1.
2.
The dotted line shows the waveform when synchronous DRAM in another CS space
is accessed.
The DACKn waveform shown is for the case where active-high has been specified.
Figure 16.22 Synchronous DRAM Read Bus Cycle
(RCD = 2 Cycles, CAS Latency = 2 Cycles, Bursts = 4)
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