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| SH7604 Datasheet, PDF (528/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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Tp
Tpw
Tr
Tc
Td1
Td4
CKIO
Upper
address
Lower
address
BS
CSn
RD/WR
WE
RD
WEn
CASxx
DQMxx
D31âD0
tRWD
DACKn
WAIT
RAS
CE
CAS
OE
CKE
tRASD1
tRASD1
Note: The DACKn waveform shown is for the case where active-high has been specified.
Figure 16.26 Synchronous DRAM Read Bus Cycle (Bank Active, Different Row Access,
TRP = 2 Cycles, RCD = 1 Cycle, CAS Latency = 1 Cycle)
512
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