SH7604 Datasheet, PDF (218/633 Pages) Hitachi Semiconductor – Hardware Manual

access is completed. The partial-share master mode only shares CS2 space with external devices.
For the CS2 space, the mode is slave mode; for other spaces, the bus is held constantly without
any bus arbitration. Which CS space of the chip in master mode the CS2 space of the chip in
partial-share master mode is allocated to, is determined by external circuitry.
Master or slave mode can be specified using external mode pins. Partial-share master mode is
reached from master mode by a software setting. See Section 3, Oscillator Circuits and Operating
Modes, for the external mode pin settings. When a device in master or slave mode does not have
the bus, the bus goes to high impedance, so the master mode chip and slave mode chips can be
connected directly. In the partial-share master mode, the bus is always driven, so an external
buffer is needed to connect to a master bus. In master mode, a connection to an external device
requesting the bus can be substituted for the slave mode connection. In the following explanation,
external devices requesting the bus are also called slaves.
The SH7604 has two internal bus masters, the CPU and the DMAC. When synchronous DRAM,
DRAM or pseudo-SRAM is connected and refresh control is performed, the refresh request
becomes a third master. In addition to these, there are also bus requests from external devices
while in the master mode. The priority for bus requests when they occur simultaneously is, highest
to lowest, refresh requests, bus requests from external devices, DMAC and CPU.
When the bus is being passed between slave and master, all bus control signals are negated before
the bus is released to prevent erroneous operation of the connected devices. Once the bus is
received, the bus control signals change from negated to bus driven. The master and slave passing
the bus between them drive the same signal values, so output buffer conflict is avoided. Turning
the output buffer off for the bus control signals on the side that releases the bus and on at the side
acquiring the bus can eliminate the high impedance period of the signals. It is usually not
necessary to insert a pull-up resistance into these control signals to prevent malfunction caused by
external noise while they are at high impedance.
Bus permission is granted at the end of the bus cycle. When the bus is requested, the bus is
released immediately if there is no ongoing bus cycle. If there is a current bus cycle, the bus is not
released until the bus cycle ends. Even when there does not appear to be an ongoing bus cycle
when seen from outside the SH7604, it cannot be determined whether or not the bus will be
released immediately when a bus control signal such as a CSn signal is seen, since an internal bus
cycle, such as inserting a wait between access cycles, may have been started. The bus cannot be
released during burst transfers for cache fills or 16-byte DMAC block transfers. Likewise, the bus
cannot be released between the read and write cycles of a TAS instruction. Arbitration is also not
performed between multiple bus cycles produced by a data width smaller than the access size,
such as a longword access to an 8-bit data width memory. Bus arbitration is performed between
external vector fetch, PC save, and SR save cycles during interrupt handling, which are all
independent accesses.
Because the CPU in the SH7604 is connected to cache memory by a dedicated internal bus, cache
memory can be read even when the bus is being used by another bus master on the chip or
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