SH7604 Datasheet, PDF (107/633 Pages) Hitachi Semiconductor – Hardware Manual

5.3.3 Vector Number Setting Register WDT (VCRWDT)
Vector number setting register WDT (VCRWDT) is a 16-bit read/write register that sets the WDT
interval interrupt and BSC compare match interrupt vector numbers (0–127). VCRWDT is
initialized to H'0000 by a reset. It is not initialized in standby mode.
Bit: 15
14
13
12
11
10
9
8
Bit name: — WITV6 WITV5 WITV4 WITV3 WITV2 WITV1 WITV0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: — BCMV6 BCMV5 BCMV4 BCMV3 BCMV2 BCMV1 BCMV0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W R/W R/W R/W R/W
• Bits 15, 7—Reserved: These bits always read 0. The write value should always be 0.
• Bits 14 to 8—Watchdog Timer (WDT) Interval Interrupt Vector Number (WITV6–WITV0):
These bits set the vector number for the interval interrupt (ITI) of the watchdog timer (WDT).
There are seven bits, so the value can be set between 0 and 127.
• Bits 6 to 0—Bus State Controller (BSC) Compare Match Interrupt Vector Number (BCMV6–
BCMV0): These bits set the vector number for the compare match interrupt (CMI) of the bus
state controller (BSC). There are seven bits, so the value can be set between 0 and 127.
5.3.4 Vector Number Setting Register A (VCRA)
Vector number setting register A (VCRA) is a 16-bit read/write register that sets the SCI receive-
error interrupt and receive-data-full interrupt vector numbers (0–127). VCRA is initialized to
H'0000 by a reset. It is not initialized in standby mode.
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