SH7604 Datasheet, PDF (408/633 Pages) Hitachi Semiconductor – Hardware Manual

1. Set the TME bit in the watchdog timer’s WTCSR register to 0.
2. Set the overflow time in bits CKS2 to CKS0 bits in the watchdog timer’s WTCSR register
(overflow time should be calculated using the clock frequency after modification).
3. After the SLEEP instruction is executed and standby mode is entered, apply a low level from
the CKPREQ/CKM pin.
4. When the chip is internally ready to modify the operating clock, a low level is output from the
CKPACK pin.
5. After the CKPACK pin goes low, the clocks are stopped and the frequency is modified. The
internal chip state is the same as in standby mode.
6. When the clock pause state (standby) is canceled, the WDT starts to count up at the falling
edge or rising edge of the NMI pin (when the NMIE bit of INTC is set).
7. When a frequency is modified, the CKPACK pin goes high after the time set by the WDT, and
the clock pause function gives external notification that the chip can again be operated
(standby mode is canceled).
8. When a clock is halted, the clock is applied again to the CKIO pin and NMI input is generated.
After the time set by the WDT, the CKPACK pin goes high, and the clock pause function gives
external notification that the chip can again be operated (standby mode is canceled).
The standby state, all internal functions and all pin states during clock pause are equivalent to
those of the normal standby mode. Figure 14.2 shows the timing chart for the clock pause
function.
Clock frequency modification
CKIO input
CKPREQ/CKM input
CKPACK output
Clock pause request cancellation
NMI input
Waiting for
clock pause
NMI
WDT
exception
setting time ^handling
Standby time
Figure 14.2 Clock Pause Function Timing
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