SH7604 Datasheet, PDF (268/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 9.7 Supported DMA Transfers
Destination
Source
External
Device with
DACK
External
Memory
On-Chip
Memory-Mapped Peripheral
External Device Module
External device with DACK
Not available Single
Single
Not available
External memory
Single
Dual
Dual
Dual
Memory-mapped external device Single
Dual
Dual
Dual
On-chip peripheral module
Not available Dual
Dual
Dual*
Single: Single address mode
Dual: Dual address mode
Note: Access size enabled by the register of the on-chip peripheral module that is the source or
destination (excludes DMAC, BSC, and UBC).
Address Modes:
• Single Address Mode
In single address mode, both the transfer source and destination are external; one (selectable) is
accessed by a DACK signal while the other is accessed by address. In this mode, the DMAC
performs the DMA transfer in one bus cycle by simultaneously outputting a transfer request
acknowledge DACK signal to one external device to access it while outputting an address to
the other end of the transfer. Figure 9.6 shows an example of a transfer between external
memory and external device with DACK. The external device outputs data to the data bus
while that data is written in external memory in the same bus cycle.
SH7604
External address bus External data bus
DMAC
External
memory
External device
with DACK
DACK
DREQ
: Data flow
Figure 9.6 Data Flow in Single Address Mode
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