SH7604 Datasheet, PDF (242/633 Pages) Hitachi Semiconductor – Hardware Manual

Address array read:
31 28
Address 011
—
3
19
9
30
Entry
address
—
6
4
31 28
9
3 210
Data —
Tag address
LRU — V —
3
19
6 11 2
Address array write:
31 28
Address 011
3
Tag address
19
9
3 210
Entry
address
—V
—
6 11 2
31
Data
9
30
—
LRU
information
—
22
6
4
V: Valid bit
Figure 8.11 Address Array Access
8.5 Cache Use
8.5.1 Initialization
Cache memory is not initialized in a reset. Therefore, the cache must be initialized by software
before use. Cache initialization clears (to 0) the address array valid bit and all LRU information.
The address array write function can be used to initialize each line, but it is simpler to initialize it
once by writing 1 to the CP bit in CCR. Figure 8.12 shows how to initialize the cache.
MOV.W
MOV.B
AND
MOV.B
OR
MOV.B
OR
MOV.B
#H'FE92, R1
@R1, R0
;
#H'FE, R0 ;
#R0, @R1 ; Cache disable
#H'10, R0
R0, @R1
; Cache purge
#H'01, R0
R0, R1
; Cache enable
Figure 8.12 Cache Initialization
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