SH7604 Datasheet, PDF (53/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 2.13 Arithmetic Instructions (cont)
Instruction
Instruction Code
Operation
Execution
States
T Bit
SUB Rm,Rn
0011nnnnmmmm1000 Rn–Rm → Rn
1
—
SUBC Rm,Rn
0011nnnnmmmm1010 Rn–Rm–T → Rn,
1
Borrow → T
Borrow
SUBV Rm,Rn
0011nnnnmmmm1011 Rn–Rm → Rn,
1
Underflow → T
Underflow
Note: The normal minimum number of execution cycles. (The number in parentheses is the
number of cycles when there is contention with preceding or following instructions.)
Table 2.14 Logic Operation Instructions
Instruction
Instruction Code
AND Rm,Rn
0010nnnnmmmm1001
AND #imm,R0
11001001iiiiiiii
AND.B #imm,@(R0,GBR) 11001101iiiiiiii
NOT
OR
OR
OR.B
Rm,Rn
0110nnnnmmmm0111
Rm,Rn
0010nnnnmmmm1011
#imm,R0
11001011iiiiiiii
#imm,@(R0,GBR) 11001111iiiiiiii
TAS.B @Rn
0100nnnn00011011
TST Rm,Rn
0010nnnnmmmm1000
TST #imm,R0
11001000iiiiiiii
TST.B #imm,@(R0,GBR) 11001100iiiiiiii
XOR Rm,Rn
0010nnnnmmmm1010
XOR #imm,R0
11001010iiiiiiii
XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
Operation
Execu-
tion
States
Rn & Rm → Rn
1
R0 & imm → R0
1
(R0 + GBR) & imm → 3
(R0 + GBR)
~Rm → Rn
1
Rn | Rm → Rn
1
R0 | imm → R0
1
(R0 + GBR) | imm →
3
(R0 + GBR)
If (Rn) is 0, 1 → T; 1 → 4
MSB of (Rn)
Rn & Rm; if the result is 1
0, 1 → T
R0 & imm; if the result is 1
0, 1 → T
(R0 + GBR) & imm; if the 3
result is 0, 1 → T
Rn ^ Rm → Rn
1
R0 ^ imm → R0
1
(R0 + GBR) ^ imm →
3
(R0 + GBR)
T Bit
—
—
—
—
—
—
—
Test
result
Test
result
Test
result
Test
result
—
—
—
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