SH7604 Datasheet, PDF (315/633 Pages) Hitachi Semiconductor – Hardware Manual

11.2.3 Input Capture Register (ICR)
Bit: 15
14
13
…
3
2
1
0
Bit name:
…
Initial value: 0
0
0
…
0
0
0
0
R/W: R
R
R
…
R
R
R
R
ICR is a 16-bit read-only register. When a rising edge or falling edge of the input capture signal is
detected, the current FRC value is transferred to ICR. At the same time, the input capture flag
(ICF) in FTCSR is set to 1. The edge of the input signal can be selected using the input edge select
bit (IEDGA) in TCR.
Because ICR is a 16-bit register, data transfers involving the CPU are performed via a temporary
register (TEMP). See Section 11.3, CPU Interface, for more detailed information. To ensure that
the input capture operation is reliably performed, set the pulse width of the input capture input
signal to six system clocks (φ) or more.
ICR is initialized to H'0000 by a reset, in standby mode, and when the module standby function is
used.
11.2.4 Timer Interrupt Enable Register (TIER)
Bit: 7
6
5
4
3
2
1
0
Bit name: ICIE
—
—
— OCIAE OCIBE OVIE
—
Initial value: 0
0
0
0
0
0
0
1
R/W: R/W
—
—
—
R/W R/W R/W
—
TIER is an 8-bit read/write register that controls enabling of all interrupt requests. TIER is
initialized to H'01 by a reset, in standby mode, and when the module standby function is used.
• Bit 7—Input Capture Interrupt Enable (ICIE): Selects enabling/disabling of the ICI interrupt
request when the input capture flag (ICF) in FTCSR is set to 1.
Bit 7: ICIE
0
1
Description
Interrupt request (ICI) caused by ICF disabled
Interrupt request (ICI) caused by ICF enabled
(Initial value)
• Bits 6 to 4—Reserved: These bits always read 0. The write value should always be 0. Do not
write 1.
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