SH7604 Datasheet, PDF (306/633 Pages) Hitachi Semiconductor – Hardware Manual

The dividend register L for 32-bit division (DVDNT) is a 32-bit read/write register in which the
32-bit dividend used for 32-bit ÷ 32-bit division operations is written. When 32-bit ÷ 32-bit
division is run, the value set as the dividend is lost and the quotient written at the end of division.
When this register is written to, the same value is written in the DVDNTL register. The MSB
written is sign-extended in the DVDNTH register. Writing to this register starts the 32-bit ÷ 32-bit
division operation. It is not initialized by a power-on reset or manual reset, in standby mode, or
during module standbys.
10.2.3 Division Control Register (DVCR)
Bit: 31
30
29
…
3
2
1
0
Bit name: —
—
—
…
—
— OVFIE OVF
Initial value: 0
0
0
…
0
0
0
0
R/W: R
R
R
…
R
R
R/W R/W
The division control register (DVCR) is a 32-bit read/write register, but is also 16-bit accessible. It
controls enabling/disabling of the overflow interrupt. This register is initialized to H'00000000 by
a power-on reset or manual reset. It is not initialized in standby mode or during module standbys.
• Bits 31 to 2: Reserved. These bits always read 0. The write value should always be 0.
• Bit 1: OVF Interrupt Enable (OVFIE): Selects enabling or disabling of the OVF interrupt
request (OVFI) upon overflow.
Bit 1: OVFIE
Description
0
Interrupt request (OVFI) caused by OVF disabled
(Initial value)
1
Interrupt request (OVFI) caused by OVF enabled
Note: Always set the OVFIE bit before starting the operation whenever executing interrupt
handling for overflows.
• Bit 0: Overflow Flag (OVF). Flag indicating an overflow has occurred.
Bit 0: OVF
0
1
Description
No overflow has occurred
Overflow has occurred
(Initial value)
290