SH7604 Datasheet, PDF (72/633 Pages) Hitachi Semiconductor – Hardware Manual

Bits 2–7 are reserved. They always read 0, and the write value should always be 0.
Modifying Frequencies: In the following modifications, the device is running in clock modes 0 to
3, and the operating frequency is left unchanged, doubled, or quadrupled using PLL circuit 2.
• Set the TME bit to 0 in or above the oscillation settling time that specifies the on-chip WDT’s
overflow time.
• Set the frequency modification register to the target value. (The chip will go internally to
standby mode temporarily.)
• All circuits involved in oscillation operate and the clock is supplied to the WDT. The WDT
overflows with this clock.
• When the WDT overflows, a clock at the frequency set within the chip begins to be supplied
and the chip returns from standby mode.
Frequency Modification Guidelines:
• Only write to the frequency modification register while the cache is disabled.
• The frequency modification program is always in cache memory and so should be executed
utilizing the forced access space of the data array. Figure 3.7 shows how the frequency
modification register is set.
• When the frequency modification program is executed, execute an associative or forced purge
of the entries in the data array used.
• Place at least eight consecutive NOP instructions after an instruction that writes to the
frequency modification register.
Disable cache
Transfer the frequency
modification program
to the data array
Cache purge
Execute the frequency
modification program in
data array forced space
Next program
Figure 3.7 Frequency Modification Flowchart
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