SH7604 Datasheet, PDF (273/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 9.8 Relationship of Request Modes and Bus Modes by DMA Transfer Category
Address
Mode
Transfer Category
Request
Mode
Transfer
Bus Size
Mode (Bytes)
Single External device with DACK and external memory External
B/C 1/2/4
External device with DACK and memory-mapped External
external device
B/C 1/2/4
Dual
External memory and external memory
All^*1
B/C 1/2/4/16
External memory and memory-mapped external All^*1
device
B/C 1/2/4/16
Memory-mapped external device and memory- All^*1
mapped external device
B/C 1/2/4/16
External memory and on-chip peripheral module All^*2
B/C^*3 1/2/4/16^*4
Memory-mapped external device and on-chip
All^*2
peripheral module
B/C^*3 1/2/4/16^*4
On-chip peripheral module and on-chip peripheral All^*2
module
B/C^*3 1/2/4/16^*4
B: Burst, C: Cycle-steal
Notes: 1. External requests and auto-requests are both available. The SCI cannot be specified as
the transfer request source, however, except for on-chip peripheral module requests.
2. External requests, auto-requests and on-chip peripheral module requests are all
available. When the SCI is the transfer request source, however, the transfer
destination or transfer source must be the SCI.
3. If the transfer request source is the SCI, cycle-steal (C) only (DREQ by edge detection,
active low).
4. The access size is that permitted by the register of the on-chip peripheral module that is
the transfer destination or source.
Bus Mode and Channel Priority: When a given channel (1) is transferring in burst mode and
there is a transfer request to a channel (0) with a higher priority, the transfer of the channel with
higher priority (0) will begin immediately. When channel 0 is also operating in the burst mode, the
channel 1 transfer will continue as soon as the channel 0 transfer has completely finished. When
channel 0 is in cycle-steal mode, channel 1 will begin operating again after channel 0 completes
the transfer of one transfer unit, but the bus will then switch between the two in the order channel
1, channel 0, channel 1, channel 0. Since channel 1 is in burst mode, it will not give the bus to the
CPU. This example is illustrated in Figure 9.12.
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