SH7604 Datasheet, PDF (36/633 Pages) Hitachi Semiconductor – Hardware Manual

Delayed Branch Instructions: Unconditional branch instructions are delayed. Executing the
instruction that follows the branch instruction, before branching reduces pipeline disruption during
branching (table 2.3).
Table 2.3 Delayed Branch Instructions
SH7604 Series CPU
BRA TRGET
ADD R1,R0
Description
Executes ADD before
branching to TRGET
Example of Conventional CPU
ADD.W R1,R0
BRA
TRGET
Multiply and Multiply-and-Accumulate Operations: 16-bit × 16-bit → 32-bit multiply
operations are executed in one to two states. 16-bit × 16-bit + 64-bit → 64-bit multiply-and-
accumulate operations are executed in two to three states. 32-bit × 32-bit → 64-bit multiply and
32-bit × 32-bit + 64bit → 64-bit multiply-and-accumulate operations are executed in two to four
states.
T Bit: The T bit in the status register changes according to the result of the comparison, and in
turn is the condition (true/false) that determines if the program will branch (table 2.4). The number
of instructions that change the T bit is kept to a minimum to improve the processing speed.
Table 2.4 T Bit
SH7604 CPU
CMP/GE R1,R0
BT
TRGET0
BF
TRGET1
ADD
CMP/EQ
BT
#–1,R0
#0,R0
TRGET
Description
T bit is set when R0 ≥ R1. The
program branches to TRGET0
when R0 ≥ R1 and to TRGET1
when R0 < R1.
T bit is not changed by ADD.
T bit is set when R0 = 0.
The program branches if R0 = 0.
Example of Conventional CPU
CMP.W R1,R0
BGE
TRGET0
BLT
TRGET1
SUB.W
BEQ
#1,R0
TRGET
Immediate Data: Byte (8-bit) immediate data resides in the instruction code. Word or longword
immediate data is not input via instruction codes but is stored in a memory table. An immediate
data transfer instruction (MOV) accesses the memory table using the PC relative with
displacement addressing mode (table 2.5).
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