SH7604 Datasheet, PDF (223/633 Pages) Hitachi Semiconductor – Hardware Manual

During a manual reset, the values of the bus state controller setting registers are held, so they do
not need to be set again.
Partial-share master mode is designed to be used with a chip in master mode. Figure 7.52 shows
an example of connections between a partial-share master mode and master mode SH7604. On the
master mode side, the CS3 space is connected to synchronous DRAM and the CS0 space to ROM.
On the partial-share master mode side, the CS0 space is connected to ROM, the master side
synchronous DRAM is connected to the CS2 space, and the CS3 space is connected to dedicated
synchronous DRAM. The partial-share master is also connected through the CS2 space to the
master synchronous DRAM so it can be accessed. The master, however, cannot access devices on
the partial-share master side. There is a buffer for addresses and control signals and a buffer for
data located between the partial-share master and the master. They are controlled by a buffer
control circuit. The buffers latch signals synchronous to the clock rise and match timing, so an AC
operating margin is assured. When the master side synchronous DRAM is read from the partial-
share master, however, address and control line output requires an extra cycle, and input of read
data requires an extra cycle. The CAS latency setting within the bus controller should be 2 higher
than the actual synchronous DRAM CAS latency. If the clock cycle is sufficiently long relative to
the time for addresses, control signals and write signals from the partial-share master to reach the
synchronous DRAM on the master side through the buffer and to the time for read data from the
synchronous DRAM on the master side to reach the partial-share master through the buffer, if the
respective setup time limits can be satisfied, then there is no need to delay by one cycle clock
signal synchronously with the clock. In this case, the previously described latch is not needed.
When a processor in the partial-share master mode accesses the CS2 space, it performs the
following procedure. The BREQ signal is asserted at the clock fall to request the bus from the
master. The BACK signal is sampled at every clock fall, and when an assertion is received, the
access cycle starts at the next clock rise. After the access ends, BREQ is negated at the clock fall.
Control of the buffer when a CS2 space device is being accessed from the partial-share master
references the BREQ and BACK signals. Notification that the bus is enabled for use is conducted
by the BACK connected to the partial-share master, but the BACK signal may be negated while
the bus is in use when the master requires the bus back to service a refresh or the like. For this
reason, the BREQ signal must be monitored to see whether the partial-share master can continue
using the bus after BACK is asserted. For address buffers, after the address buffer is turned on by
the detection of a BACK assertion, the buffer remains on until BREQ is negated. When BREQ is
negated, the buffer goes off. When the buffer is slow going off and it conflicts with the start of the
access cycle at the master, the BREQ signal output from the partial-share master as part of the
buffer control circuit must be delayed a clock and input to the BRLS signal.
When the bus is released after the CS2 space is accessed in partial-share master mode, the bus will
be released after waiting for the time required for auto-precharge if the CS2 space was
synchronous DRAM. Other spaces always have the bus themselves, so there is no precharge of
CS3 space memory upon release after a CS2 space bus request, even when DRAM, synchronous
DRAM or pseudo-SRAM is connected to the CS3 space. Partial-share master mode does not
refresh CS2 (it is ignored).
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