SH7604 Datasheet, PDF (282/633 Pages) Hitachi Semiconductor – Hardware Manual

Clock
DACK
Address
bus
Column
address
DMAC read or write
(basic timing)
Figure 9.29 DACK Output in DRAM Burst Accesses
(Same Row Address, AM = 1 or 0)
Clock
DACK
Address
bus
Pre- Row
charge address
Column address
DMAC read or write
(basic timing)
Figure 9.30 DACK Output in DRAM Burst Accesses
(Different Row Address, AM = 1 or 0)
Acknowledge Signal Output when External Memory Is Set as Pseudo-SRAM: When external
memory is set as pseudo-SRAM , the acknowledge signal is output synchronous to the DMAC
address for both reads and writes (figures 9.31–9.33).
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