SH7604 Datasheet, PDF (402/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 14.1 Power-Down Modes
State
Mode
Transition
Condition
CPU,
MULT, UBC,
Clock Cache BSC
FRT, SCI,
DMAC, DIV,
INTC, WDT, Pins
Canceling
Procedure
Sleep
mode
SLEEP
instruction
executed with
SBY bit set to 0
in SBYCR
Runs
Halted Runs
Runs
Runs
1. Interrupt
2. DMA
address
error
3. Power-
on reset
4. Manual
reset
Standby
mode
SLEEP
instruction
executed with
SBY bit set to 1
in SBYCR
Halted
Halted
Held
Halted
Held or high 1. NMI
impedance interrupt
2. Power-
on reset
3. Manual
reset
Module MSTP bit for Runs
standby relevant module
function is set to 1
Run Runs
(MULT
is held)
When
FRT and
MSTP bit SCI pins
is 1, the are
supply of initialized,
the clock to and others
the relevant operate.
module is
halted.
Clear MSTP
bit to 0
14.1.2 Register
Table 14.2 shows the register configuration.
Table 14.2 Register Configuration
Name
Standby control register
Abbreviation
SBYCR
R/W Initial Value
R/W H'60
Address
H'FFFFFE91
386