SH7604 Datasheet, PDF (299/633 Pages) Hitachi Semiconductor – Hardware Manual

9.3.8 DMA Transfer End
The DMA transfer ending conditions vary when channels end individually and when both
channels end together.
Conditions for Channels Ending Individually: When either of the following conditions are met,
the transfer will end in the relevant channel only:
• The value of the channel’s DMA transfer count register (TCR) becomes 0.
When the TCR value becomes 0, the DMA transfer for that channel ends and the transfer-end
flag bit (TE) is set in CHCR. If the IE (interrupt enable) bit has already been set, a DMAC
interrupt (DEI) request is sent to the CPU. In 16-byte transfer, when the TCR is 3,2,1 during
the final transfer, the source address will be output four times, but the destination address will
only be output the number of times found in TCR before transfer ends.
• The DE bit of the DMA channel control register (CHCR) is cleared to 0.
When the DMA enable bit (DE) in CHCR is cleared, DMA transfers in the affected channel
are halted. The TE bit is not set when this happens.
Source
Source
Source
address address address
first time second time third time
Source Destination Destination
address address address
fourth time first time second time
CPU
TCR = 0
(transfer ends normally)
Figure 9.52 16-Byte Transfer when TCR = 2
Conditions for Both Channels Ending Simultaneously: Transfers on both channels end when
either of the following conditions is met:
• The NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in DMAOR.
When an NMI interrupt or DMAC address error occurs and the NMIF or AE bit is set to 1 in
DMAOR, all channels stop their transfers. The DMA source address register (SAR),
designation address register (DAR), and transfer count register (TCR) are all updated by the
transfer immediately preceding the halt. When this transfer is the final transfer, TE = 1 and the
transfer ends. To resume transfer after NMI interrupt exception handling or address error
exception handling, clear the appropriate flag bit. When the DE bit is then set to 1, the transfer
on that channel will restart. To avoid this, keep its DE bit at 0. In dual address mode, DMA
transfer will be halted after the completion of the following write cycle even when the address
error occurs in the initial read cycle. SAR, DAR and TCR are updated by the final transfer.
283