SH7604 Datasheet, PDF (92/633 Pages) Hitachi Semiconductor – Hardware Manual

4.6.2 Immediately after an Interrupt-Disabled Instruction
When an instruction immediately following an interrupt-disabled instruction is decoded, interrupts
are not accepted. Address errors are accepted.
4.7 Stack Status after Exception Handling
The status of the stack after exception handling ends is as shown in table 4.11.
Table 4.11 Stack Status after Exception Handling
Type
Stack Status
Address error
SP → Address of instruction after executed instruction
32 bits
SR
32 bits
Trap instruction
SP → Address of instruction after TRAPA instruction
32 bits
SR
32 bits
General illegal instruction SP → Start address of illegal instruction
32 bits
SR
32 bits
Interrupt
SP → Address of instruction after executed instruction
32 bits
SR
32 bits
Illegal slot instruction
SP → Jump destination address of delayed branch instruction 32 bits
SR
32 bits
4.8 Usage Notes
4.8.1 Value of Stack Pointer (SP)
The value of the stack pointer must always be a multiple of four, otherwise an address error will
occur when the stack is accessed during exception handling.
4.8.2 Value of Vector Base Register (VBR)
The value of the vector base register must always be a multiple of four, otherwise an address error
will occur when the vector table is accessed during exception handling.
76