SH7604 Datasheet, PDF (318/633 Pages) Hitachi Semiconductor – Hardware Manual

Bit 0: CCLRA
0
1
Description
FRC clear disabled
FRC cleared on compare match A
(Initial value)
11.2.6 Timer Control Register (TCR)
Bit: 7
6
5
4
3
2
1
0
Bit name: IEDGA —
—
—
—
—
CKS1 CKS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
TCR is an 8-bit read/write register that selects the input edge for input capture and selects the
input clock for FRC. TCR is initialized to H'00 by a reset, in standby mode, and when the module
standby function is used.
• Bit 7—Input Edge Select (IEDG): Selects whether to capture the input capture input (FTI) on
the falling edge or rising edge.
Bit 7: IEDG
0
1
Description
Input captured on falling edge
Input captured on rising edge
(Initial value)
• Bits 6 to 2—Reserved: These bits always read 0. The write value should always be 0. Do not
write 1.
• Bits 1 and 0—Clock Select (CKS1, CKS0): These bits select whether to use an external clock
or one of three internal clocks for input to FRC. The external clock is counted at the rising
edge.
Bit 1: CKS1
0
1
Bit 0: CKS0
0
1
0
1
Description
Internal clock: count at φ/8
Internal clock: count at φ/32
Internal clock: count at φ/128
External clock: count at rising edge
(Initial value)
302