SH7604 Datasheet, PDF (317/633 Pages) Hitachi Semiconductor – Hardware Manual

Bit 7: ICF
0
1
Description
Clear conditions: When ICF is read while set to 1, and then 0 is
written to it
(Initial value)
Set conditions: When the FRC value is sent to ICR by the input
capture signal
• Bits 6 to 4—Reserved: These bits always read 0. The write value should always be 0.
• Bit 3—Output Compare Flag A (OCFA): Status flag that indicates when the values of the FRC
and OCRA match. This flag is cleared by software and set by hardware. It cannot be set by
software.
Bit 3: OCFA
0
1
Description
Clear conditions: When OCFA is read while set to 1, and then 0 is
written to it
(Initial value)
Set conditions: When the FRC value becomes equal to OCRA
• Bit 2—Output Compare Flag B (OCFB): Status flag that indicates when the values of FRC and
OCRB match. This flag is cleared by software and set by hardware. It cannot be set by
software.
Bit 2: OCFB
0
1
Description
Clear conditions: When OCFB is read while set to 1, and then 0 is
written to it
(Initial value)
Set conditions: When the FRC value becomes equal to OCRB
• Bit 1—Timer Overflow Flag (OVF): Status flag that indicates when FRC overflows (from
H'FFFF to H'0000). This flag is cleared by software and set by hardware. It cannot be set by
software.
Bit 1: OVF
0
1
Description
Clear conditions: When OVF is read while set to 1, and then 0 is
written to it
(Initial value)
Set conditions: When the FRC value changes from H'FFFF to H'0000
• Bit 0—Counter Clear A (CCLRA): Selects whether or not to clear FRC on compare match A
(signal indicating match of FRC and OCRA).
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