SH7604 Datasheet, PDF (128/633 Pages) Hitachi Semiconductor – Hardware Manual

Bits 31–0: BAMAn
0
1
n = 31 to 0
Description
Channel A break address BAAn is included in the break conditions
(Initial value)
Channel A break address BAAn is masked and therefore not included
in the break conditions
6.2.3 Break Bus Cycle Register A (BBRA)
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
Bit name:
Initial value:
R/W:
7
CPA1
0
R/W
6
CPA0
0
R/W
5
IDA1
0
R/W
4
IDA0
0
R/W
3
RWA1
0
R/W
2
RWA0
0
R/W
1
SZA1
0
R/W
0
SZA0
0
R/W
The break bus cycle register A (BBRA) is a 16-bit read/write register that selects the following
four channel A break conditions:
1. CPU cycle/peripheral cycle
2. Instruction fetch/data access
3. Read/write
4. Operand size
A power-on reset initializes BBRA to H'0000. Its value is undefined after a manual reset.
• Bits 15 to 8—Reserved: These bits always read 0. The write value should always be 0.
• Bits 7 and 6—CPU Cycle/Peripheral Cycle Select A (CPA1, CPA0): These bits select whether
to break channel A on a CPU and/or peripheral bus cycle. Peripheral cycles are defined as on-
chip DMAC bus cycles, and external bus master bus cycles when the bus is released. When the
peripheral cycle setting is made, on-chip DMAC cycles are always included in the break
conditions; however, external bus master cycles can be included or excluded, according to the
setting of the EBBE bit in the BRCR register.
112