SH7604 Datasheet, PDF (287/633 Pages) Hitachi Semiconductor – Hardware Manual

Transfer width: 16-byte
Transfer bus mode: Cycle-steal mode
Transfer address mode: Dual mode
DREQ detection method: Edge detection
DACK output timing: DMAC read and write cycles
Bus cycle: Basic bus cycle
Clock
*¹
DREQ
1st acceptance
DACK
*¹
2nd acceptance
2 cycles
Bus
cycle
CPU
DMAC 2
DMAC 4
*²
*³
*³
*³
*³
DMAC 1
DMAC 3
Notes
1. Request detection
2. When a write (dual) occurs at DACK output, the cycle is a DMAC read.
Otherwise, the cycle is a CPU cycle.
3. When DACK is output in a write (dual), the cycle is a DMAC write; when in a read
(dual), the cycle is a DMAC read.
Figure 9.38 DREQ Pin Input Detection Timing in Cycle-Steal Mode with Edge
Detection (2)
Requests can be detected 2 cycles after DACK output. After that point, the request is input to
DREQ. (If input prior to that point, a request may or may not be detected, depending on the
internal state.) DACK is output synchronous to all 4 transfers (figure 9.38).
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