SH7604 Datasheet, PDF (68/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 3.3 Clock Mode Pin Settings and States
Pin*¹
Clock
CKPREQ/
Mode MD2 MD1 MD0 CKM
EXTAL XTAL
CKIO
Internal Clock
0
0
0
0
0
1
Clock
input
Open
Output
Crystal Crystal
oscillation oscillation
Synchronized to a
phase difference of
0˚ from CKIO by PLL
circuit 1
1
0
0
1
0
1
Clock
input
Open
Output
Crystal Crystal
oscillation oscillation
Synchronized to a
phase difference of
90˚ from CKIO by
PLL circuit 1
2
0
1
0
0
1
Clock
input
Open
Output CKIO
Crystal Crystal
oscillation oscillation
3
0
1
1
0
1
Clock Open High
input
impe-
Crystal Crystal ^dance
oscillation oscillation
PLL circuit 2 output
4
1
0
0
*²
Open
Open
Clock
input
Synchronized to a
phase difference of
0˚ from CKIO by PLL
circuit 1
5
101
Open
Open
Clock
input
Synchronized to a
phase difference of
90˚ from CKIO by
PLL circuit 1
6
110
Open
Open
Clock
input
CKIO
Notes: 1. Do not use in combinations other than those listed.
2. In clock modes 4, 5, and 6, CKPREQ/CKM functions as the clock pause request pin.
3. For TBP-176 package products, only clock mode 4, 5, or 6 can be selected.
3.2.3 Connecting a Crystal Resonator
Connecting a Crystal Resonator: Figure 3.2 shows how to connect a crystal resonator. Use the
value shown in table 3.4 for the damping resistance Rd. The crystal resonator should be an AT-cut
parallel-resonance type. Be sure to connect load capacitors (CL1, CL2) as shown in the figure.
52