SH7604 Datasheet, PDF (262/633 Pages) Hitachi Semiconductor – Hardware Manual

Start
Initial settings
(SAR, DAR, TCR, CHCR,
VCRDMA, DRCR, DMAOR)
DE,
DME = 1 and NMIF, ^No
AE, TE = 0?
Yes
Has a
transfer request been ^No
generated?*¹
Yes
Transfer
TCR-1 → TCR,
SAR, and DAR updated
No
TCR = 0?
Yes
DEI interrupt request
(when IE = 1)
NMIF = 1 or
AE = 1, or DE = 0, or
No
DME = 0?
Yes
TE = 1
*²
Bus
*³
mode, transfer
request mode, DREQ detec-
tion method?
*⁴
16-byte transfer
*⁵
in progress?
NMIF = 1,
No
or AE = 1, or DE = 0,
or DME
= 0?
Yes
Transfer aborted
TE = 1
End transfer
End normally
Notes: 1. In auto-request mode, the transfer will start when the NMIF, AE, and TE bits are all 0
and the DE and DME bits are then set to 1.
2. In burst mode, DREQ = level detection (external request), or cycle-steal mode.
3. In burst mode, DREQ = edge detection (external request), or auto-request mode in
burst mode.
4. 16-byte transfer cycle in progress.
5. End of a 16-byte transfer cycle.
Figure 9.2 DMA Transfer Flow
246