SH7604 Datasheet, PDF (381/633 Pages) Hitachi Semiconductor – Hardware Manual

Transmitting
processor
Serial communication line
Receiving
processor A
(ID = 01)
Receiving
processor B
(ID = 02)
Receiving
processor C
(ID = 03)
Receiving
processor D
(ID = 04)
Serial
data
H'01
(MPB = 1)
H'AA
(MPB = 0)
ID transmit cycle =
receiving station
specification
MPB: Multiprocessor bit
Data transmit cycle =
data transmission to
receiving station specified
by ID
Figure 13.9 Example of Communication among Processors Using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A)
Communication Formats: Four formats are available. Parity-bit settings are ignored when the
multiprocessor format is selected. For details see table 13.8.
Clock: See the description in the asynchronous mode section.
Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for
transmitting multiprocessor serial data. The procedure for transmitting multiprocessor serial data is
as follows:
1. SCI status check and transmit data write: read the serial status register (SSR), check that the
TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set the MPBT
(multiprocessor bit transfer) bit to 0 or 1 in SSR. Finally, clear TDRE to 0.
2. To continue transmitting serial data, read the TDRE bit to check whether it is safe to write (if it
reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a
transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and
cleared automatically.
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