SH7604 Datasheet, PDF (431/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 15.9 Bus Timing With PLL Off (CKIO Output) [Mode 2] (cont)
(Conditions: V_CC = 5.0 V ±10%, Ta = –20 to +75°C)
Item
Symbol Min
Max
Unit Figures
WAIT setup time
t_WTS
22
—
ns 15.19, 15.43, 15.55,
15.67, 15.70
WAIT hold time
t_WTH
5
—
ns 15.19, 15.43, 15.55,
15.67, 15.70
RAS delay time 1 (SDRAM) t_RASD1
—
18
ns 15.38
RAS delay time 3 (DRAM) t_RASD3
3
18
ns 15.47
CAS delay time 1 (SDRAM) t_CASD1
—
18
ns 15.38
CAS delay time 3 (DRAM) t_CASD3
3
18
ns 15.47
DQM delay time
t_DQMD
—
18
ns 15.38
CKE delay time
t_CKED
—
21
ns 15.37
CE delay time 2
t_CED2
3
18
ns 15.60
OE delay time 2
t_OED2
—
18
ns 15.60
IVECF delay time
t_IVD
—
18
ns 15.69
Address input setup time^* t_ASIN
14
—
ns 15.71
Address input hold time^* t_AHIN
3
—
ns 15.71
BS input setup time^*
t_BSS
15
—
ns 15.71
BS input hold time^*
t_BSH
3
—
ns 15.71
Read/write input setup time^* t_RWS
15
—
ns 15.71
Read/write input hold time^* t_RWH
3
—
ns 15.71
Data buffer on time
t_DON
—
18
ns 15.17, 15.39, 15.48,
15.61
Data buffer off time
t_DOF
—
18
ns 15.17, 15.39, 15.48,
15.61
Address hold time 2
t_AH2
5
—
ns 15.17
Note: When the external addresses monitor function is used, the PLL must be on.
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