SH7604 Datasheet, PDF (270/633 Pages) Hitachi Semiconductor – Hardware Manual

• Dual Address Mode
In dual address mode, both the transfer source and destination are accessed (selectable) by
address. The source and destination can be located externally or internally. The DMAC
accesses the source in the read cycle and the destination in the write cycle, so the transfer is
performed in two separate bus cycles. The transfer data is temporarily stored in the DMAC.
Figure 9.8 shows an example of a transfer between two external memories in which data is
read from one memory in the read cycle and written to the other memory in the following write
cycle.
SH7604
DMAC
External data bus
2
External
memory
External
memory
1
: Data flow
1: Read cycle
2: Write cycle
Figure 9.8 Data Flow in Dual Address Mode
In dual address mode transfers, external memory, memory-mapped external devices and on-
chip peripheral modules can be mixed without restriction. Specifically, this enables transfers
between the following:
1. External memory and external memory.
2. External memory and memory-mapped external devices.
3. Memory-mapped external devices and memory-mapped external devices.
4. External memory and on-chip peripheral modules (excluding the DMAC, BSC, and UBC).
5. Memory-mapped external devices and on-chip peripheral modules (excluding the DMAC,
BSC, and UBC). The access size is that is enabled by the register of the on-chip peripheral
module that is the source or destination (excludes the DMAC, BSC, and UBC).
6. On-chip peripheral modules (excluding the DMAC, BSC, and UBC) and on-chip
peripheral modules (excluding the DMAC, BSC, and UBC).
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