SH7604 Datasheet, PDF (190/633 Pages) Hitachi Semiconductor – Hardware Manual

7.5.7 Refreshes
The bus state controller is equipped with a function to control refreshes of synchronous DRAM.
Auto-refreshes can be performed by setting the MCR’s RMD bit to 0 and the RFSH bit to 1. When
the synchronous DRAM is not accessed for a long period of time, set the RFSH bit and RMODE
bit both to 1 to initiate self-refresh mode, which uses low power consumption to retain data.
Auto-Refresh: Refreshes are performed at the interval determined by the input clock selected by
the CKS2–CKS0 bits in RTCSR and the value set in RTCOR. Set the CKS2–CKS0 bits and
RTCOR so that the refresh interval specifications of the synchronous DRAM being used are
satisfied. First, set RTCOR, RTCNT and the RMODE and RFSH bits in MCR, then set the CKS2–
CKS0 bits. When a clock is selected with the CKS2–CKS0 bits, RTCNT starts counting up from
the value at that time. The RTCNT value is constantly compared to the RTCOR value and a
request for a refresh is made when the two match, starting an auto-refresh. RTCNT is cleared to 0
at that time and the count up starts again. Figure 7.25 shows the timing for the auto-refresh cycle.
First, a PALL command is issued during the Tp cycle to change all the banks from active to
precharge states. A REF command is then issued in the Trr cycle. After the Trr cycle, no new
commands are output for the number of cycles specified in the TRAS bit in MCR + 2 cycles. The
TRAS bit must be set to satisfy the refresh cycle time specifications (active/active command delay
time) of the synchronous DRAM. When the MCR’s TRP bit is 1, an NOP cycle is inserted
between the Tp cycle and Trr cycle.
During a manual reset, no refresh request is issued, since there is no RTCNT count-up. To perform
a refresh properly, make the manual reset period shorter than the refresh cycle interval and set
RTCNT to (RTCOR – 1) so that the refresh is performed immediately after the manual reset is
cleared.
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