SH7604 Datasheet, PDF (180/633 Pages) Hitachi Semiconductor – Hardware Manual

7.5.4 Single Reads
When a cache area is accessed and there is a cache miss, the cache fill cycle is performed in 16-
byte units. This means that all the data read in the burst read is valid. Since the required data when
a cache-through area is accessed has a maximum length of 32 bits, however, the remaining 12
bytes are wasted. The same kind of wasted data access is produced when synchronous DRAM is
specified as the source in a DMA transfer by the DMAC and the transfer unit is other than 16
bytes. Figure 7.17 shows the timing of a single address read. Because the synchronous DRAM is
set to the burst read/single write mode, the read data output continues after the required data is
received. To avoid data conflict, an empty read cycle is performed from Td2 to Td4 after the
required data is read in Td1 and the device waits for the end of synchronous DRAM operation. In
this case, data is only fetched in Td1, so the BS signal is asserted for Td1 only.
When the data width is 16 bits, the number of burst transfers during a read is 8. BS is asserted and
data fetched in cache-through and other DMA read cycles only in the Td1 and Td2 cycles (of the 8
cycles from Td1 to Td8) for longword accesses, and only in the Td1 cycle for word or byte
accesses.
Empty cycles tend to increase the memory access time, lower the program execution speed, and
lower the DMA transfer speed, so it is important to avoid accessing unnecessary cache-through
areas and to use data structures that enable 16-byte unit transfers by placing data on 16-byte
boundaries when performing DMA transfers that specify synchronous DRAM as the source.
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