 English |
|
|
|
|
|
|
|
| SH7604 Datasheet, PDF (289/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
| |||
| ◁ |
Clock
*1
DREQ
1st acceptance
DACK
3 cycles
*2
2 cycles
Area where 2nd
acceptance is possible
Bus cycle
CPU
CPU H
CPU L
DMAC H DMAC L
Notes: 1. Request detection
2. Request detection not established.
Figure 9.40 Changing the Bus Size of a 16-Bit External Device
Clock
*1
DREQ
1st acceptance 3 cycles
DACK
*2
2 cycles
Area where 2nd
acceptance is possible
Bus
cycle
CPU HL
CPU LL
DMAC HL
DMAC LL
CPU HH
CPU LH
DMAC HH
DMAC LH
Notes: 1. Request detection
2. Request detection not established.
Figure 9.41 Changing the Bus Size of an 8-Bit External Device
273
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese