SH7604 Datasheet, PDF (425/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 15.6 Bus Timing With PLL On [Mode 0, 4] (cont)
(Conditions: V_CC = 5.0 V ±10%, Ta = –20 to +75°C)
Item
DACK delay time 1
Symbol
t_DACD1
DACK delay time 2
t_DACD2
WAIT setup time
t_WTS
WAIT hold time
t_WTH
RAS delay time 1 (SDRAM) t_RASD1
RAS delay time 2 (DRAM) t_RASD2
CAS delay time 1 (SDRAM) t_CASD1
CAS delay time 2 (DRAM) t_CASD2
DQM delay time
t_DQMD
CKE delay time
t_CKED
CE delay time 1
t_CED1
OE delay time 1
t_OED1
IVECF delay time
t_IVD
Address input setup time t_ASIN
Address input hold time
t_AHIN
BS input setup time
t_BSS
BS input hold time
t_BSH
Read/write input setup time t_RWS
Read/write input hold time t_RWH
Address hold time 1
t_AH1
Min
—
—
20
5
—
1/2 tcyc + 3
—
1/2 tcyc + 3
—
—
1/2 tcyc + 3
—
—
14
3
15
3
15
3
5
Max
Unit Figures
18
ns 15.14, 15.20, 15.40,
15.52, 15.66
1/2 tcyc + 18 ns 15.14, 15.20, 15.40,
15.52, 15.66
—
ns 15.19, 15.43, 15.55,
15.66, 15.70
—
ns 15.19, 15.43, 15.55,
15.66, 15.70
18
ns 15.20
1/2 tcyc + 18 ns 15.40
18
ns 15.20
1/2 tcyc + 18 ns 15.40
18
ns 15.20
21
ns 15.37
1/2 tcyc + 18 ns 15.52
1/2 tcyc + 18 ns 15.52
18
ns 15.68
—
ns 15.71
—
ns 15.71
—
ns 15.71
—
ns 15.71
—
ns 15.71
—
ns 15.71
—
ns 15.15
409