SH7604 Datasheet, PDF (235/633 Pages) Hitachi Semiconductor – Hardware Manual

8.4.2 Write Access
This cache is of the write-through type, and writing to external memory is performed regardless of
whether or not there is a cache hit. The write address output to the cache address bus is used to
compare to the tag address of the cache’s address array. When they match, the write data output to
the cache data bus in the following cycle is written to the data array. When they do not match,
nothing is written to the cache data array. The write address is output to the internal address bus 1
cycle later than the cache address bus. The write data is similarly output to the internal data bus 1
cycle later than the cache data bus. The CPU waits until the writes onto the internal bus are
completed.
CPU pipeline stage
Cache address bus
Cache data bus
Internal address bus
Internal data bus
EX: Instruction execution
MA: Memory access
EX
MA
EX
MA
Address A Address B
Cache tag comparison
Address A
Data array write
Address A
Address B
Address B
Address A
Figure 8.5 Write Access
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