SH7604 Datasheet, PDF (87/633 Pages) Hitachi Semiconductor – Hardware Manual

4.3 Address Errors
4.3.1 Sources of Address Errors
Address errors occur when instructions are fetched or data read or written, as shown in table 4.6.
Table 4.6 Bus Cycles and Address Errors
Bus Cycle
Type
Bus
Master Bus Cycle Description
Address Errors
Instruction CPU
fetch
Instruction fetched from even address
Instruction fetched from odd address
None (normal)
Address error occurs
Instruction fetched from other than on-chip peripheral None (normal)
module space
Instruction fetched from on-chip peripheral module
space
Address error occurs
Data
CPU or Word data accessed from even address
read/write DMAC _{Word data accessed from odd address}
None (normal)
Address error occurs
Longword data accessed from a longword boundary None (normal)
Longword data accessed from other than a longword Address error occurs
boundary
Access of cache purge space, address array read/
write space or on-chip I/O space by PC-relative
addressing
Address error occurs
Access of cache purge space, address array read/
write space, data array read/write space or on-chip
I/O space by a TAS.B instruction
Address error occurs
Byte data accessed in on-chip peripheral module
space at addresses H'FFFFFF00 to H'FFFFFFFF
Address error occurs
Word or longword data accessed in on-chip peripheral None (normal)
module space at addresses H'FFFFFF00 to
H'FFFFFFFF
Longword data accessed in on-chip peripheral module Address error occurs
space at addresses H'FFFFFE00 to H'FFFFFEFF
Word or byte data accessed in on-chip peripheral
module space at addresses H'FFFFFE00 to
H'FFFFFEFF
None (normal)
Notes: 1. Address errors do not occur during the synchronous DRAM mode register write cycle.
2. 16-byte DMAC transfers use longword accesses.
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