SH7604 Datasheet, PDF (329/633 Pages) Hitachi Semiconductor – Hardware Manual

11.7 Usage Notes
Note that the following contention and operations occur when the FRT is operating:
1. FRC operates on the timer drive clock (φ/4), which has a cycle of 4 times the system clock (φ).
For this reason, when the CPU performs an access, both the CPU and FRT will be operating,
so a WAIT request will be generated from the FRT to the CPU. The number of access cycles
thus varies by between 3 and 12 cycles.
2. Contention between FRC Write and Clear
When a counter clear signal is generated with the timing shown in figure 11.14 during the
write cycle for the lower byte of FRC, writing does not occur to the FRC, and the FRC clear
takes priority.
Timer drive
clock
FRC lower-byte write cycle
Address
Internal write
signal
Counter clear
signal
FRC address
FRC
N
H'0000
Figure 11.14 Contention between FRC Write and Clear
3. Contention between FRC Write and Increment
When an increment occurs with the timing shown in figure 11.15 during the write cycle for the
lower byte of FRC, no increment is performed and the counter write takes priority.
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