SH7604 Datasheet, PDF (622/633 Pages) Hitachi Semiconductor – Hardware Manual

DMAC
DMA operation register (DMAOR) H'FFFFFFB0
32
Bit
Item
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit Name — — — — — — — — — — — — — — — —
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
RRRR RRRR RRRR RRR
Item
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name — — — — — — — — — — — — PR AE NMIF DME
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
R R R R R R R R R R R R R/W R/ R/ R/W
(W)* (W)*
Note: Only 0 can be written, to clear the flag.
Bit
Bit Name
Value
Description
3 Priority mode bit (PR)
0 Fixed priority (Ch 0 > Ch 1) (Initial value)
1 Round-robin mode (High priority switches to low after
each transfer)
(The priority for the first DMA transfer after a reset is
Ch 1 > Ch 0)
2 Address error flag bit
0 No DMAC address error (Initial value)
(AE)
1 Address error by DMAC
1 NMI flag bit (NMIF)
0 No NMIF interrupt (Initial value)
To clear the NMIF bit, read 1 from it and then write 0
1 NMIF has occurred
0 DMA master enable bit 0 DMA transfers disabled on all channels (Initial value)
(DME)
1 DMA transfers enabled on all channels
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