SH7604 Datasheet, PDF (294/633 Pages) Hitachi Semiconductor – Hardware Manual

DREQ Pin Input Detection Timing in Burst Mode: In burst mode, the request detection timing
differs when DREQ input is detected by edge and when detected by level.
When DREQ input is detected by edge, once a request is detected, DMA transfers continue until
the conditions for ending the transfers are met, regardless of the state of the DREQ pin thereafter.
During this period, requests cannot be detected. When the transfer start conditions are met after a
transfer ends, requests can be detected again for each cycle.
When DREQ input is detected by level, whenever a request is detected for the same channel as in
the next request detection cycle, that channel is executed continuously. When no request is input,
however, the bus cycles of other channels and other bus masters are executed.
• Burst Mode, Single Mode, Level Detection
Acknowledge signals for request signals are output 3 cycles later at the earliest. Even when the
request signal is dropped within 2 cycles of the output of this acknowledge signal, the fourth or
fifth requests in figure 9.46 are accepted. This means that 4 or 5 DMA transfers are executed
even when the request for the 1st acknowledge signal drops out.
Transfer width: Byte, word, longword
Transfer bus mode: Burst mode
Transfer address mode: Single mode
DREQ detection method: Level detection
DACK output timing: DMAC cycle
Bus cycle: Basic bus cycle
Clock
DREQ
***
1st
2nd 3rd
accept- accept- accept-
ance ance ance
Bus
cycle
DACK
*
4th
accept-
ance
*
5th
accept-
ance
*
6th
accept-
ance
DMAC read 1 DMAC read 2 DMAC read 3 DMAC read 4 DMAC read 5 DMAC read 6
Note: Request detection (The points when the acceptances occur vary with the type of wait.)
Figure 9.46 Timing of DREQ Pin Input Detection in Burst Mode with Level Detection (1)
(Data Transfer from Normal Space to Device)
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