SH7604 Datasheet, PDF (221/633 Pages) Hitachi Semiconductor – Hardware Manual

CKIO
BRLS
BGR
Bus request Bus release
Refresh request
Figure 7.49 Case in Which BGR is Negated
Case in Which BGR is Not Negated: If access processing for an external device has been
initiated before the refresh request is generated, and the device is waiting to acquire the bus, the
BGR signal will not be negated. After the BRLS signal is negated, refreshing begins after
completion of the access involving the external device that was waiting for the bus.
CKIO
BRLS
BGR
Bus request Bus release
Refresh request
Figure 7.50 Case in Which BGR is Not Negated
When the SH7604 is being used in slave mode, the bus is released as soon as the bus access cycle
ends, but in the case of a slave designed by the user, multiple consecutive bus accesses may be
attempted in order to reduce the arbitration overhead. To ensure dependable refreshing in this case,
the design should provide for the bus to be released to prevent the slave holding the bus for longer
than the refresh cycle.
7.10.2 Slave Mode
In slave mode, the bus is usually released. External devices cannot be accessed unless the bus
arbitration sequence is performed to capture the bus. During a reset, the bus is released and the bus
arbitration sequence starts from the reset vector fetch.
The BREQ signal is asserted (to low level) synchronously with the clock fall for capturing the bus.
The assertion of the BACK signal (to low level) is sampled at the clock fall. When a BACK
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