SH7604 Datasheet, PDF (150/633 Pages) Hitachi Semiconductor – Hardware Manual

7.1.4 Register Configuration
The BSC has seven registers. These registers are used to control wait states, bus width, interfaces
with memories like DRAM, synchronous DRAM, pseudo-SRAM, and burst ROM, and DRAM,
synchronous DRAM, and pseudo-SRAM refreshing. The register configurations are shown in
table 7.2.
The size of the registers themselves is 16 bits. If read as 32 bits, the upper 16 bits are 0. In order to
prevent writing mistakes, 32-bit writes are accepted only when the value of the upper 16 bits of the
write data is H'A55A; no other writes are performed. Initialize the reserved bits.
Initialization Procedure: Do not access a space other than CS0 until the settings for the interface
to memory are completed.
Table 7.2 Register Configuration
Name
Abbr. R/W Initial Value Address*¹ Access Size
Bus control register 1
BCR1 R/W H'03F0
H'FFFFFFE0 16^*2, 32
Bus control register 2
BCR2 R/W H'00FC
H'FFFFFFE4 16^*2, 32
Wait control register
WCR
R/W H'AAFF
H'FFFFFFE8 16^*2, 32
Individual memory control register MCR
R/W H'0000
H'FFFFFFEC 16^*2, 32
Refresh timer control/status register RTCSR R/W H'0000
H'FFFFFFF0 16^*2, 32
Refresh timer counter
RTCNT R/W H'0000
H'FFFFFFF4 16^*2, 32
Refresh time constant register
RTCOR R/W H'0000
H'FFFFFFF8 16^*2, 32
Notes: 1. This address is for 32-bit accesses; for 16-bit accesses add 2.
2. 16-bit access is for read only.
7.1.5 Address Map
The SH7604 address map, which has a memory space of 256 Mbytes, is divided into four spaces.
The types and data width of devices that can be connected are specified for each space. The
overall space address map is shown in table 7.3. Since the spaces of the cache area and the cache-
through area are the same, the maximum memory space that can be connected is 128 Mbytes. This
means that when address H'20000000 is accessed in a program, the data accessed is actually in
H'00000000.
There are several spaces for cache control. These include the associative purge space for cache
purges, address array read/write space for reading and writing addresses (address tags), and data
array read/write space for forced reads and writes of data arrays.
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