SH7604 Datasheet, PDF (291/633 Pages) Hitachi Semiconductor – Hardware Manual

Transfer width: 16-byte
Transfer bus mode: Cycle-steal mode
Transfer address mode: Dual mode
DREQ detection method: Level detection
DACK output timing: DMAC write cycle
Bus cycle: Basic bus cycle
Clock
*1
DREQ
3 cycles
1st acceptance
DACK
Bus
cycle
CPU
CPU
*2
2nd acceptance
2 cycles
DMAC
read 2
DMAC
read 4
DMAC
write 1
DMAC
write 3
DMAC
read 1
DMAC
read 3
Invalid
write
DMAC
write 2
DMAC
write 4
Notes: 1. Request detection
2. Request detection not established.
Figure 9.43 Timing of DREQ Pin Input Detection in Cycle Steal Mode
with Level Detection (3)
Requests can be detected for the first time 3 cycles after the bus cycle prior to the DMAC read
cycle and starts sometime between then and 2 cycles after DACK output (figure 9.43). This varies
with variations in waits and the like. This means that if request output is stopped within 3 cycles
from the bus cycle prior to the DMAC read cycle, the next DMA transfer is not performed; if
request output is stopped within 2 cycles of DACK output, the next DMA transfer may sometimes
be performed.
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