SH7604 Datasheet, PDF (146/633 Pages) Hitachi Semiconductor – Hardware Manual

• Master and slave modes (bus arbitration)
 Total master and partial-share master modes. In total master mode, all resources are shared
with other CPUs. Bus permission is shared when an external bus release request is
received. In partial-share master mode, only the CS2 space is shared with other CPUs; all
other spaces can be accessed at any time.
 In slave mode, the external bus is accessed when a bus use request is output and bus use
permission is received.
• Refresh counter can be used as an interval timer
 Interrupt request generated upon compare match (CMI interrupt request signal).
7.1.2 Block Diagram
Figure 7.1 shows the BSC block diagram.
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