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| SH7604 Datasheet, PDF (565/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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CKIO
Upper
address
Lower
address
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
DACKn
Tp
Tr
tAD
Tc1
Tc2
Tc1
Tc2
tAD
tAD
tBSD
tCSD1
tRWD
tBSD
tBSD
tBSD
tCSD1
tRWD
tWED2 tWED2
tWED2
tWDD
tDON
tWDD
tWDH1
tWDH3
tWED2
tDOF
tWDH1
tWDH3
tDACD1
tDACD3 tDACD1
tDACD3
WAIT
RAS,
CE
CAS,
OE
tCED2
tCED2
CKE
Note: The DACKn waveform shown is for the case where active-high has been specified.
Figure 16.63 Pseudo-SRAM Write Cycle
(Static Column Mode, PLL Off, TRP = 1 Cycle, RCD = 1 Cycle, No Waits)
549
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