SH7604 Datasheet, PDF (272/633 Pages) Hitachi Semiconductor – Hardware Manual

DREQ
Bus
cycle
Bus right returned to CPU
CPU
CPU CPU DMAC DMAC CPU DMAC DMAC CPU
Read Write
Read Write
Figure 9.10 DMA Transfer Timing in Cycle-Steal Mode
(Dual Address Mode, DREQ Level Detection)
• Burst Mode
In burst mode, once the DMAC gets the bus, the transfer continues until the transfer end
condition is satisfied. When external request mode is used with level detection of the DREQ
pin, however, negating DREQ will pass the bus to the other bus master after completion of the
bus cycle of the DMAC that currently has an acknowledged request, even if the transfer end
conditions have not been satisfied. Burst mode cannot be used when the transfer request
originates from the serial communication interface (SCI).
Figure 9.11 shows an example of DMA transfer timing in burst mode (single address mode,
DREQ level detection).
DREQ
Bus
cycle
CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Figure 9.11 DMA Transfer Timing in Burst Mode (Single Address Mode, DREQ Level
Detection)
Refreshes cannot be performed during a burst transfer, so ensure that the number of transfers
satisfies the refresh request period when a memory requiring refreshing is used.
Relationship of Request Modes and Bus Modes by DMA Transfer Category: Table 9.8 shows
the relationship between request modes, bus modes, etc., by DMA transfer category.
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