SH7604 Datasheet, PDF (434/633 Pages) Hitachi Semiconductor – Hardware Manual

CKIO
A26–A0
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31–D0
DACKn
T₁
t_AD
T₂
t_AD
t_BSD
t_BSD
t_CSD1
t_CSD3
t_RWD
t_RWD
t_RSD2
t_RSD2
t_WES1
t_RDS2
t_RDH2
t_DACD1
t_DACD3
WAIT
RAS,
CE
CAS,
OE
Notes: 1.
2.
3.
CKE
The dotted line shows the waveform when synchronous DRAM is connected.
t_RDH2 is specified from the rise of CSn or RD, whichever is first.
The DACKn waveform shown is for the case where active-high has been specified.
Figure 15.16 Basic Read Cycle (No Waits, PLL Off)
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