SH7604 Datasheet, PDF (116/633 Pages) Hitachi Semiconductor – Hardware Manual

5.5 Interrupt Response Time
Table 5.8 shows the interrupt response time, which is the time from the occurrence of an interrupt
request until interrupt exception handling starts and fetching of the first instruction of the interrupt
service routine begins. Figure 5.7 shows the pipeline when an IRL interrupt is accepted.
Table 5.8 Interrupt Response Time
Number of States
Item
Peripheral
NMI Module
IRL
Notes
Compare identified inter- 2
5
—
rupt priority with SR mask
level
Wait for completion of
X (≥ 0)
sequence currently being
executed by CPU
The longest sequence is
for interrupt or address-
error exception handling
(X = 4 + m1 + m2 + m3 +
m4). If an interrupt-
masking instruction
follows, however, the
time may be even longer.
Time from interrupt
5 + m1 + m2 + m3
—
exception handling (SR
and PC saves and vector
address fetch) until fetch
of first instruction of
exception service routine
starts
Interrupt
response
Total: 7 + m1 + m2 + m3
Minimum: 10
10 + m1 + m2 + m3 —
13
—
Maximum: 11 + 2 (m1 + m2 + 14 + 2 (m1 + m2 + —
m3) + m4
m3) + m4
Note:
m1–m4 are the number of states needed for the following memory accesses
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch of first instruction of interrupt service routine
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