SH7604 Datasheet, PDF (503/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 16.5 Control Signal Timing (cont)
(Conditions: V_CC = 3.0 to 5.5 V, Ta = –20 to +75°C)
Item
Symbol Min
Max
Unit Figure
BREQ delay time 1 (PLL on)
t_BRQD1
BACK setup time 1 (PLL on)
t_BAKS1
BACK hold time 1 (PLL on)
t_BAKH1
BREQ delay time 1 (PLL on, 1/4 cycle delay) t_BRQD1
BACK setup time 1 (PLL on, 1/4 cycle delay) t_BAKS1
BACK hold time 1 (PLL on, 1/4 cycle delay) t_BAKH1
BREQ delay time 2 (PLL off)
t_BRQD2
BACK setup time 2 (PLL off)
t_BAKS2
BACK hold time 2 (PLL off)
t_BAKH2
—
1/2 tcyc + 25 ns
1/2 tcyc + 20 —
ns
15 – 1/2 tcyc —
ns
—
3/4 tcyc + 25 ns
1/4 tcyc + 20 —
ns
15 – 1/4 tcyc —
ns
—
40
ns
20
—
ns
30
—
ns
16.12
16.12
16.13
Bus tri-state delay time 1 (PLL on)
Bus buffer on time 1 (PLL on)
t_BOFF1 0
t_BON1 0
35
ns 16.10,
33
ns ^16.12
Bus tri-state delay time 1 (PLL on, 1/4 cycle t_BOFF1
delay)
Bus buffer on time 1 (PLL on, 1/4 cycle delay) t_BON1
1/4 tcyc
1/4 tcyc
1/4 tcyc + 35 ns 16.10,
1/4 tcyc + 33 ns ^16.12
Bus tri-state delay time 1 (PLL off)
Bus buffer on time 1 (PLL off)
t_BOFF1 0
t_BON1 0
45
ns 16.11,
40
ns ^16.13
Bus tri-state delay time 2 (PLL on)
Bus buffer on time 2 (PLL on)
t_BOFF2
t_BON2
1/2 tcyc
1/2 tcyc
1/2 tcyc + 35 ns
1/2 tcyc + 33 ns
16.10,
16.12
Bus tri-state delay time 2 (PLL on, 1/4 cycle t_BOFF2
delay)
Bus buffer on time 2 (PLL on, 1/4 cycle delay) t_BON2
3/4 tcyc
3/4 tcyc
3/4 tcyc + 35 ns 16.10,
3/4 tcyc + 33 ns ^16.12
Bus tri-state delay time 3 (PLL off)
Bus buffer on time 3 (PLL off)
t_BOFF3 0
t_BON3 0
45
ns 16.11,
40
ns ^16.13
487