SH7604 Datasheet, PDF (284/633 Pages) Hitachi Semiconductor – Hardware Manual

Acknowledge Signal Output When External Memory Is Set as Burst ROM: When external
memory is set as burst ROM, the acknowledge signal is output synchronous to the DMAC address
(no dual writes allowed) (figure 9.34).
Clock
DACK
Address
bus
DMAC cycle
DMAC cycle
DMAC (1 wait state)
Figure 9.34 DACK Output in Nibble Accesses of Burst ROM
9.3.7 DREQ Pin Input Detection Timing
In external request mode, DREQ pin signals are usually detected at the rising edge of the clock
pulse (CKIO). When a request is detected, a DMAC bus cycle is produced three cycles later at the
earliest and a DMA transfer performed. After the request is detected, the timing of the next input
detection varies with the bus mode, address mode, method of DREQ input detection, and the
memory connected.
DREQ Pin Input Detection Timing in Cycle-Steal Mode:
In cycle-steal mode, once a request is detected from the DREQ pin, request detection for the next
DMA transfer cannot be performed for a certain period of time. After request detection has again
become possible, detectable cycles continue until a request is detected.
Figure 9.35 illustrates the timing from the detection of a request till the next time requests are
detectable.
• Cycle-Steal Mode Edge Detection
Requests can be detected 2 cycles after DACK output. After that point, the request is input to
DREQ. (If input prior to that point, a request may or may not be detected, depending on the
internal state.)
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