SH7604 Datasheet, PDF (176/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 7.4 SZ and AMX Bits and Address Multiplex Output
Setting
External Address Pins
SZ AMX2 AMX1 AMX0 Output Timing A1–A8 A9 A10 A11 A12 A13
10
0
0
Column address A1–A8 A9 A10 A11 L/H^*1 A21^*2
Row address
A9–A16 A17 A18 A19 A20 A21^*2
10
0
1
Column address A1–A8 A9 A10 A11 L/H^*1 A22^*2
Row address
A10–A17 A18 A19 A20 A21 A22^*2
10
1
0
Column address A1–A8 A9 A10 A11 L/H^*1 A23^*2
Row address
A11–A18 A19 A20 A21 A22 A23^*2
10
1
1
Column address A1–A8 A9 L/H^*1 A19^*2 A12 A13
Row address
A9–A16 A17 A18 A19^*2 A20 A21
11
1
1
Column address A1–A8 A9 L/H^*1 A18^*2 A12 A13
Row address
A9–A16 A17 A17 A18^*2 A20 A21
00
0
0
Column address A1–A8 A9 A10 L/H^*1 A20^*2 A13
Row address
A9–A16 A17 A18 A19 A20^*2 A21
00
1
1
Column address A1–A8 L/H^*1 A18^*2 A11 A12 A13
Row address
A9–A16 A17 A18^*2 A19 A20 A21
01
1
1
Column address A1–A8 L/H^*1 A17^*2 A11 A12 A13
Row address
A9–A16 A16 A17^*2 A19 A20 A21
AMX2–AMX0 settings of 100, 101 and 110 are reserved, so do not use them. When SZ = 0, the
settings 001 and 010 are reserved as well, so do not use them either.
Notes: 1. L/H is a bit used to specify commands. It is fixed at L or H according to the access
mode.
2. Specifies bank address.
7.5.3 Burst Reads
Figure 7.15 shows the timing chart for burst reads. In the following example, 2 synchronous
DRAMs of 256k × 16 bits are connected, the data width is 32 bits and the burst length is 4. After a
Tr cycle that performs ACTV command output, a READA command is called in the Tc cycle and
read data is accepted at internal clock falls from Td1 to Td4. Tap is a cycle for waiting for the
completion of the auto-precharge based on the READA command within the synchronous DRAM.
During this period, no new access commands are issued to the same bank. Accesses of the other
bank of the synchronous DRAM by another CS space are possible. Depending on the TRP
specification in MCR, the SH7604 determines the number of Tap cycles and does not issue a
command to the same bank during that period.
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