SH7604 Datasheet, PDF (404/633 Pages) Hitachi Semiconductor – Hardware Manual

Bit 4: MSTP4
0
1
Description
DMAC running
Clock supply to DMAC halted
(Initial value)
• Bit 3—Module Stop 3 (MSTP3): Specifies halting the clock supply to the multiplication unit
(MULT). When the MSTP3 bit is set to 1, the supply of the clock to MULT is halted. When
the clock halts, MULT retains its pre-halt state. This bit should be set when the MULT is
halted.
Bit 3: MSTP3
0
1
Description
MULT running
Clock supply to MULT halted
(Initial value)
• Bit 2—Module Stop 2 (MSTP2): Specifies halting the clock supply to the division unit
(DIVU). When the MSTP2 bit is set to 1, the supply of the clock to DIVU is halted. When the
clock halts, the DIVU registers retain their pre-halt state. This bit should be set when the DIVU
is halted.
Bit 2: MSTP2
0
1
Description
DIVU running
Clock supply to DIVU halted
(Initial value)
• Bit 1—Module Stop 1 (MSTP1): Specifies halting the clock supply to the 16-bit free-running
timer (FRT). When the MSTP1 bit is set to 1, the supply of the clock to the FRT is halted.
When the clock halts, all FRT registers are initialized except the FRT interrupt vector register
in INTC, which holds its previous value. When MSTP1 is cleared to 0 and the FRT begins
running again, its starts operating from its initial state.
Bit 1: MSTP1
0
1
Description
FRT running
Clock supply to FRT halted
(Initial value)
• Bit 0—Module Stop 0 (MSTP0): Specifies halting the clock supply to the serial
communication interface (SCI). When the MSTP0 bit is set to 1, the supply of the clock to the
SCI is halted. When the clock halts, all SCI registers are initialized except the SCI interrupt
vector register in INTC, which holds its previous value. When MSTP0 is cleared to 0 and the
SCI begins running again, its starts operating from its initial state.
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