SH7604 Datasheet, PDF (183/633 Pages) Hitachi Semiconductor – Hardware Manual

ACTV command and READ or WRIT command, in that order, after the precharge is completed.
With successive accesses to different row addresses, the precharge is performed after the access
request occurs, so the access time is longer. When writing, performing an auto-precharge means
that no command can be called for t_RWL + t_AP cycles after a WRITA command is called. When
the bank active mode is used, READ or WRIT commands can be issued consecutively if the row
address is the same. This shortens the number of cycles by t_RWL + t_AP for each write. The number
of cycles between the issue of the precharge command and the row address strobe command is
determined by the TRP bit in MCR.
Whether execution is faster when the bank active mode is used or when basic access is used is
determined by the proportion of accesses to the same row address (P1) and the average number of
cycles from the end of one access to the next access (t_A). When tA is longer than t_AP, the delay
waiting for the precharge during a read becomes invisible. If t_A is longer than t_RWL + t_AP, the
delay waiting for the precharge also becomes invisible during writes. The difference between the
bank active mode and basic access speeds in these cases is the number of cycles between the start
of access and the issue of the read/write command: (t_RP + t_RCD) × (1 – P1) and t_RCD,
respectively.
The time that a bank can be kept active, t_RAS, is limited. When it is not assured that this period
will be provided by program execution and that another row address will be accessed without a hit
to the cache, the synchronous DRAM must be set to auto-refresh and the refresh cycle must be set
to the maximum value t_RAS or less. This enables the limit on the maximum active period for each
bank to be ensured. When auto-refresh is not being used, some measure must be taken in the
program to ensure that the bank does not stay active for longer than the prescribed period.
Figure 7.19 shows a burst read cycle that is not an auto-precharge cycle, figure 7.20 shows a burst
read cycle to a same row address, figure 7.21 shows a burst read cycle to different row addresses,
figure 7.22 shows a write cycle without auto-precharge, figure 7.23 shows a write cycle to a same
row address, and figure 7.24 shows a write cycle to different row addresses.
In figure 7.20, a cycle that does nothing, Tnop, is inserted before the Tc cycle that issues the
READ command. Synchronous DRAMs, however, have a 2 cycle latency during reads for the
DQMxx signals that specify bytes. If the Tc cycle is performed immediately without inserting a
Tnop cycle, the DQMxx signal for the Td1 cycle data output cannot be specified. This is why the
Tnop cycle is inserted. When the CAS latency is 2 or more, the Tnop cycle is not inserted so that
timing requirements will be met even when a DQMxx signal is set after the Tc cycle.
When the SH7604 is set to the bank active mode, the access will start with figure 7.19 or figure
7.22 and repeat figure 7.20 or figure 7.23 for as long as the same row address continues to be
accessed when only accesses to the respective banks of the CS3 space are considered. Accesses to
other CS spaces during this period have no effect. When an access occurs to a different row
address while the bank is active, figure 7.21 or figure 7.24 will be substituted for figures 7.20 and
7.23 after this is detected. Both banks will become inactive even in the bank active mode after the
refresh cycle ends or after the bus is released by bus arbitration.
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